Many different resistive cross point memory cell arrays have been proposed, including resistive cross point memory cell arrays having magnetic random access memory (MRAM) elements, phase change memory elements, resistive polymer memory elements, polysilicon memory elements, and write-once (e.g., fuse based or anti-fuse based) resistive memory elements.
A typical storage device, for example, an MRAM storage device, includes an array of memory cells. Word lines may extend along rows of the memory cells, and bit lines may extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and bit line. Each memory cell stores a bit of information as an orientation of a magnetization. In particular, the magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, may, for example, represent logic values of 0 and 1. The magnetization orientation affects the resistance of a memory cell. For example, the resistance of a memory cell may be first value, R, if the magnetization orientation is parallel, and the resistance of the memory cell may be increased to a second value, R+ΔR, if the magnetization orientation is changed from parallel to anti-parallel.
In general, the logic state of a resistive cross point memory cell may be read by sensing the resistance state of the selected memory cell. However, sensing the resistance state of a single memory cell in the array typically is difficult because all of the memory cells in a resistive cross point memory cell array are interconnected by many parallel paths. Thus, the resistance that is determined at one cross point equals the resistance of the memory cell at the cross point in parallel with the resistance of memory cells in the other word lines and bit lines. This means that, in an array that does not use switches or diodes to isolate memory cells from one another, the other memory cells in the same column and row may be rendered unusable. Thus, a simple shorted memory element can cause a column-wide/row-wide error. In addition, if the selected memory cell being sensed has a different resistance state due to stored magnetization, a small differential voltage may develop. This small differential voltage may give rise to parasitic or “sneak path” currents that may interfere with the sensing of the resistance state of the selected memory cell.
Thus, a need exists for the reliable isolation of selected resistive cross point memory cells while data stored on a selected memory cell is being sensed.